1. Field of the Invention
The present invention relates to the field of computers. More specifically, the present invention relates to computer architecture.
2. Description of the Related Art
Out-of-order processors issue and execute instructions out-of-order to gain performance benefits. However, data dependencies exist between certain instructions and require preservation of those dependencies. Violation of those data dependencies results in a data hazard. Two particular data hazards are read-after-write (RAW) and 2) write-after-read (WAR), also referred to as overeager load (OEL).
A store instruction writes data into a designated memory location. A load instruction reads data from a designated memory location. If the store and load instructions are accessing the same memory location and the store instruction is older than the load instruction (i.e., the store instruction precedes the load instruction in the program sequence that includes these instructions), then the load instruction may depend on the store instruction, assuming there are no other intervening store instructions. An additional factor that affects dependency between instructions includes the size of the data being written or read. Since the store instruction requires more time than a load instruction, there is a possibility that the load instruction will access the memory location before the store instruction completes. If so, then the load instruction will access stale data. To resolve this RAW data hazard without losing the benefit of out-of-order processing, RAW bypass is performed. The data being written by the store instruction is passed to the load instruction before the store instruction actually writes it to the memory location.
An OEL hazard occurs when a processor issues and executes a load instruction that depends on an older store instruction before the store instruction is issued. Again, the load instruction will read stale data because the store instruction has not written to the memory location. To avoid this data hazard, the load instruction is rewound (i.e., flushed from the execution pipeline to start over) and a dependency is imposed on the load instruction so that it does not issue until after the store instruction. In addition, some processors utilize a “coloring” technique to identify instructions with data dependencies in order to impose those data dependencies.
A conventional processor resolves these two data hazards with separate logic. The RAW logic identifies issued store instructions that are older than an issued load instruction. The OEL logic identifies issued load instructions that are younger than an issued store instruction. The processor utilizes two separate priority pickers for performing operations to resolve the two data hazards. The separate logic and separate priority pickers occupy valuable area, which becomes even more valuable as processor designs evolve to incorporate more power and functionality.